Tae Jun Ham

About Me

Education

Ph.D. in Electrical Engineering

Princeton University

Sep 2012 - Jun 2018

Advisors: Margaret Martonosi and Juan Luis Aragon
Dissertation: Efficient data accesses in accelerator-based heterogeneous architecture

Bachelor of Science in Electrical and Computer Engineering

Duke University

Aug 2009 - Dec 2011

Summa Cum Laude with Distinction in Electrical and Computer Engineering (GPA: 3.95 / 4.00)

Experience

Senior Staff Software Engineer

Google · Full-time

Sep 2021 - Present

I lead the technical strategy for fleet-wide resource efficiency and hardware/software co-design across Google's global datacenter infrastructure. My work spans the entire stack, from distributed systems to silicon microarchitecture.

• Datacenter Efficiency: Led fleet-wide optimization initiatives across compute, memory, and storage, delivering significant capacity savings.
• Hardware/Software Co-Design: Bridge distributed systems and silicon microarchitecture to evaluate, optimize, and guide the architectural design of future SoC and server platforms.
• ML for Systems: Focus on leveraging machine learning to drive system efficiency and performance, and unlock new opportunities in hardware/software co-design.

Postdoctoral Researcher

Seoul National University

Jul 2018 - Jul 2021

Focused on Computer Architecture and Systems research.
Supervisor: Jae W. Lee.
(Note: My position at Seoul National University also fulfilled my mandatory military service duty)

Research Intern

Microsoft Research

May 2016 - Aug 2016

Investigated and designed an efficient secure memory architecture featuring near-data computation.
Collaborator: Stavros Volos.

Research Intern

Intel Labs

May 2015 - Nov 2015

Conducted research and development on a custom hardware accelerator tailored for graph analytics.
Collaborator: Lisa Wu Wills.

Research Intern

AMD Research

Jun 2013 - Aug 2013

Explored heterogeneous memory systems, focusing specifically on stacked DRAM architectures and performance optimization.
Collaborator: Joseph L. Greathouse.

Research Intern

Samsung Advanced Institute of Technology

Jun 2012 - Aug 2012

Investigated GPU branch divergence problems and proposed architectural solutions to improve execution efficiency.
Collaborator: Yeon-Gon Cho.

Research Assistant

Systems Architecture Integration Lab, Duke University

Jan 2012 - May 2012

Research on efficient control and management of the heterogeneous memory system.
Advisor: Benjamin C. Lee.

Honors and Awards

• IEEE MICRO Top Picks (2021)
  Genesis paper is selected as one of top 12 computer architecture papers of 2020
• IEEE MICRO Top Picks Honorable Mention (2021)
  Graphene paper is selected as one of top 24 computer architecture papers of 2020
• ISPASS Best Paper Award Nominee (2020)
  MosaicSim paper is selected as the Best Paper Nominee in ISPASS 2020
• MICRO-49 Best Paper Award (2016)
  Graphicionado paper is selected as the Best Paper in MICRO 2016
• IEEE MICRO Top Picks Honorable Mention (2016)
  DeSC paper is selected as one of top 23 computer architecture papers of 2015
• Facebook Graduate Fellowship Finalist (2016)
• Gordon Y.S. Wu Fellowship (2012-2017), Princeton University
  Prestigious award given to top incoming graduate students.
• Samsung Scholarship (2012-2017)
  Prestigious award given to Korean students studying in US. Up to $50,000 per year for five years of graduate studies.
• Summa Cum Laude (2011), Duke University
  Latin honor given to top graduates of the class

Publications

• [EMNLP 2025]

  Reliable and Cost-Effective Exploratory Data Analysis via Graph-Guided RAG

  [Link]
  Mossad Helali, Yutai Luo, Tae Jun Ham, Jim Plotts, Ashwin Chaugule, Jichuan Chang, Parthasarathy Ranganathan, Essam Mansour
  The 2025 Conference on Empirical Methods in Natural Language Processing
• [SAC 2025]

  SkipLSM: Fast Retrieval of Hot Key-Value Pairs on LSM Tree

  [Link]
  Jongsung Lee, Sam Son, Jonghyun Bae, Yunho Jin, Tae Jun Ham, Jae W. Lee
  The 40th ACM/SIGAPP Symposium on Applied Computing
• [TOS 2024]

  An LSM tree augmented with b+ tree on nonvolatile memory

  [Link]
  Donguk Kim, Jongsung Lee, Keun Soo Lim, Jun Heo, Tae Jun Ham, Jae W. Lee
  ACM Transactions on Storage
• [ISCA@50 Retrospective]

  Genesis: A Hardware Acceleration Framework for Genomic Data Analysis

  [Link]
  Lisa Wu Wills, Tae Jun Ham, Jae W. Lee, Krste Asanovic
  The 50th Annual IEEE/ACM International Symposium on Computer Architecture (Retrospective)
• [HPCA 2022]

  Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh

  [Link]
  Michael Jaemin Kim, Jaehyun Park, Yeonhong Park, Wanju Doh, Namhoon Kim, Tae Jun Ham, Jae W. Lee, Jung Ho Ahn
  The 28th IEEE International Symposium on High-Performance Computer Architecture
  Acceptance rate: 80/262=30(%)
• [TECS 2022]

  Maphea: A framework for lightweight memory hierarchy-aware profile-guided heap allocation

  [Link]
  Deok-Jae Oh, Yaebin Moon, Do Kyu Ham, Tae Jun Ham, Yongjun Park, Jae W. Lee, Jung Ho Ahn, Eojin Lee
  ACM Transactions on Embedded Computing Systems
• [MLSys 2022]

  Ulppack: Fast sub-8-bit matrix multiply on commodity simd hardware

  [Link]
  Jaeyeon Won, Jeyeon Si, Sam Son, Tae Jun Ham, Jae W. Lee
  Proceedings of Machine Learning and Systems
• [HPCA 2022]

  Anna: Specialized architecture for approximate nearest neighbor search

  [Link]
  Yejin Lee, Hyunji Choi, Sunhong Min, Hyunseung Lee, Sangwon Baek, Dawoon Jeong, Jae W. Lee, Tae Jun Ham
  The 28th IEEE International Symposium on High-Performance Computer Architecture
  Acceptance rate: 80/262=30(%)
• [ECCV 2022]

  L3: accelerator-friendly lossless image format for high-resolution, high-throughput dnn training

  [Link]
  Jonghyun Bae, Woohyeon Baek, Tae Jun Ham, Jae W. Lee
  European Conference on Computer Vision
  Acceptance rate: 1650/5803=28(%)
• [TC 2022]

  Architecting a flash-based storage system for low-cost inference of extreme-scale dnns

  [Link]
  Yunho Jin, Shine Kim, Tae Jun Ham, Jae W. Lee
  IEEE Transactions on Computers
• [ASPLOS 2021]

  MERCI: Efficient Embedding Reduction on Commodity Hardware via Sub-Query Memoization

  [Link]
  Yejin Lee, Seong Hoon Seo, Hyunji Choi, Hyoung Uk Sul, Soosung Kim, Jae W. Lee, Tae Jun Ham
  The 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
  Acceptance rate: 75/398=19(%)
• [FAST 2021]

  FlashNeuron: SSD-Enabled Large-Batch Training of Very Deep Neural Networks

  [Link]
  Jonghyun Bae, Jongsung Lee, Yunho Jin, Sam Son, Shine Kim, Hakbeom Jang, Tae Jun Ham, Jae W. Lee
  USENIX Conference on File and Storage Technologies
  Acceptance rate: 28/130=21(%)
• [FAST 2021]

  Behemoth: A Flash-centric Training Accelerator for Extreme-scale DNNs

  [Link]
  Shine Kim, Yunho Jin, Gina Sohn, Jonghyun Bae, Tae Jun Ham, Jae W. Lee
  USENIX Conference on File and Storage Technologies
  Acceptance rate: 28/130=21(%)
• [HPCA 2021]

  Layerweaver: Maximizing Resource Utilization of Neural Processing Units via Layer-Wise Scheduling

  [Link]
  Young H. Oh, Seonghak Kim, Yunho Jin, Sam Son, Jonghyun Bae, Jongsung Lee, Yeonhong Park, Dong Uk Kim, Tae Jun Ham, Jae W. Lee
  The 27th IEEE International Symposium on High-Performance Computer Architecture
  Acceptance rate: 63/258=24(%)
• [IEEE Micro Top Picks 2021]

  Accelerating Genomic Data Analytics with Composable Hardware Acceleration Framework

  [Link]
  Tae Jun Ham, David Bruns-Smith, Brendan Sweeney, Yejin Lee, Seong Hoon Seo, U Gyeong Song, Young H. Oh, Krste Asanovic, Jae W. Lee, Lisa Wu Wills
  IEEE Micro Special Issue on Top Picks from the 2020 Computer Architecture Conferences
• [ISCA 2021]

  ELSA: Hardware-Software Co-design for Efficient, Lightweight Self-Attention Mechanism in Neural Networks

  [Link]
  Tae Jun Ham, Yejin Lee, Seong Hoon Seo, Soosung Kim, Hyunji Choi, Sung Jun Jung, Jae W. Lee
  The 48th ACM/IEEE International Symposium on Computer Architecture
  Acceptance rate: 76/406=19(%)
• [ISCA 2021]

  BOSS: Bandwidth-Optimized Search Accelerator for Storage-Class Memory

  [Link]
  Jun Heo, Seung Yul Lee, Sunhong Min, Yeonhong Park, Sung Jun Jung, Tae Jun Ham, Jae W. Lee
  The 48th ACM/IEEE International Symposium on Computer Architecture
  Acceptance rate: 76/406=19(%)
• [ATC 2021]

  ASAP: Fast Mobile Application Switch via Adaptive Prepaging

  [Link]
  Sam Son, Seung Yul Lee, Yunho Jin, Jonghyun Bae, Jinkyu Jeong, Tae Jun Ham, Jae W. Lee, Hongil Yoon
  USENIX Annual Technical Conference
  Acceptance rate: 64/341=19(%)
• [LCTES 2021]

  MaPHeA: A Lightweight Memory Hierarchy-Aware Profile-Guided Heap Allocation Framework

  [Link]
  Deok-Jae Oh, Yaebin Moon, Eojin Lee, Tae Jun Ham, Jae W. Lee, Jung Ho Ahn
  ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems
• [ISPASS 2020]

  MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems

  [Link]
  Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi
  IEEE International Symposium on Performance Analysis of Systems and Software
  Acceptance rate: 25/73=34(%) Best Paper Award Nominee
• [ASPLOS 2020]

  IIU: Specialized Architecture for Inverted Index Search

  [Link]
  Jun Heo, Jaeyeon Won, Yejin Lee, Shivam Bharuka, Jaeyoung Jang, Tae Jun Ham, Jae W. Lee
  The 25th ACM International Conference on Architectural Support for Programming Languages and Operating Systems
  Acceptance rate: 86/476=18(%)
• [HPCA 2020]

  A3: Accelerating Attention Mechanisms in Neural Networks with Approximation

  [Link]
  Tae Jun Ham, Sung Jun Jung, Seonghak Kim, Young H. Oh, Yeonhong Park, Yoonho Song, Jung-Hun Park, Sanghee Lee, Kyoung Park, Jae W. Lee, Deog-Kyoon Jeong
  The 26th IEEE International Symposium on High-Performance Computer Architecture
  Acceptance rate: 48/235=20(%)
• [ISCA 2020]

  A Specialized Architecture for Object Serialization with Applications to Big Data Analytics

  [Link]
  Jaeyoung Jang, Sung Jun Jung, Sunmin Jeong, Jun Heo, Hoon Shin, Tae Jun Ham, Jae W. Lee
  The 47th ACM/IEEE International Symposium on Computer Architecture
  Acceptance rate: 77/428=18(%)
• [ISCA 2020]

  Genesis: A Hardware Acceleration Framework for Genomic Data Analysis

  [Link]
  Tae Jun Ham, David Bruns-Smith, Brendan Sweeney, Yejin Lee, Seong Hoon Seo, U Gyeong Song, Young H. Oh, Krste Asanovic, Jae W. Lee, Lisa Wu Wills
  The 47th ACM/IEEE International Symposium on Computer Architecture
  Acceptance rate: 77/428=18(%) IEEE MICRO Top Picks (one of the top 12 computer architecture papers of 2020)
• [ISCA 2020]

  A Case for Hardware-Based Demand Paging

  [Link]
  Gyusun Lee, Wenjing Jin, Wonsuk Song, Jeonghun Gong, Jonghyun Bae, Tae Jun Ham, Jae W. Lee, Jinkyu Jeong
  The 47th ACM/IEEE International Symposium on Computer Architecture
  Acceptance rate: 77/428=18(%)
• [MICRO 2020]

  Graphene: Strong yet lightweight row hammer protection

  [Link]
  Yeonhong Park, Woosuk Kwon, Eojin Lee, Tae Jun Ham, Jung Ho Ahn, Jae W. Lee
  The 53rd IEEE/ACM International Symposium on Microarchitecture
  Acceptance rate: 82/424=19(%) IEEE MICRO Top Picks Honorable Mention (one of the top 24 computer architecture papers of 2020)
• [ICCAD 2020]

  Unlocking Wordline-Level Parallelism for Fast Inference on RRAM-Based DNN Accelerator

  [Link]
  Yeonhong Park, Seung Yul Lee, Hoon Shin, Jun Heo, Tae Jun Ham, Jae W. Lee
  The 39th IEEE/ACM International Conference on Computer-Aided Design
  Acceptance rate: 127/470=27(%)
• [TACO 2019]

  Efficient Data Supply for Parallel Heterogeneous Architectures

  [Link]
  Tae Jun Ham, Juan L. Aragón, Margaret Martonosi
  ACM Transactions on Architecture and Code Optimization
• [ATC 2019]

  Asynchronous I/O Stack: A Low-latency Kernel I/O Stack for Ultra-Low Latency SSDs

  [Link]
  Gyusun Lee, Seokha Shin, Wonsuk Song, Tae Jun Ham, Jae W. Lee, Jinkyu Jeong
  USENIX Annual Technical Conference
  Acceptance rate: 71/356=20(%)
• [ATC 2019]

  Practical Erase Suspension for Modern Low-latency SSDs

  [Link]
  Shine Kim, Jonghyun Bae, Hakbeom Jang, Wenjing Jin, Jeonghun Gong, Seungyeon Lee, Tae Jun Ham, Jae W. Lee
  USENIX Annual Technical Conference
  Acceptance rate: 71/356=20(%)
• [MICRO 2019]

  Charon: Specialized near-memory processing architecture for clearing dead objects in memory

  [Link]
  Jaeyoung Jang, Jun Heo, Yejin Lee, Jaeyeon Won, Seonghak Kim, Sung Jun Jung, Hakbeom Jang, Tae Jun Ham, Jae W. Lee
  The 52nd IEEE/ACM International Symposium on Microarchitecture
  Acceptance rate: 79/344=23(%)
• [IEEE Micro 2019]

  SSDStreamer: Specializing I/O Stack for Large-Scale Machine Learning

  [Link]
  Jonghyun Bae, Hakbeom Jang, Jeonghun Gong, Wenjing Jin, Shine Kim, Jaeyoung Jang, Tae Jun Ham, Jinkyu Jeong, Jae W. Lee
  IEEE Micro, Sep/Oct 2019
• [TACO 2017]

  Decoupling data supply from computation for latency-tolerant communication in heterogeneous architectures

  [Link]
  Tae Jun Ham, Juan L. Aragón, Margaret Martonosi
  ACM Transactions on Architecture and Code Optimization
• [MICRO 2016]

  Graphicionado: A High-Performance and Energy-Efficient Accelerator for Graph Analytics

  [Link]
  Tae Jun Ham, Lisa Wu, Narayanan Sundaram, Nadathur Satish, Margaret Martonosi
  The 49th IEEE/ACM International Symposium on Microarchitecture
  Acceptance rate: 61/283=22(%) Best Paper Award
• [MICRO 2015]

  DeSC: Decoupled Supply-Compute Communication Management for Heterogeneous Architectures

  [Link]
  Tae Jun Ham, Juan L. Aragón, Margaret Martonosi
  The 48th IEEE/ACM International Symposium on Microarchitecture
  Acceptance rate: 61/283=22(%) IEEE MICRO Top Picks Honorable Mention (Top 23 computer architecture papers of 2015) • Motivated $5.8 million DARPA-funded DECADES project
• [HPCA 2013]

  Disintegrated control for energy-efficient and heterogeneous memory systems

  [Link]
  Tae Jun Ham, Bharath K. Chelepalli, Neng Xue, Benjamin C. Lee
  The 19th IEEE International Symposium on High-Performance Computer Architecture
  Acceptance rate: 51/249=20(%)

Patents

• Apparatus and method with scheduling

  [Link]
  Jae Wook Lee, Younghwan Oh, Yunho Jin, Tae Jun Ham
  US Patent 12,524,267 (2026)
• Scheduler, method of operating the same, and accelerator apparatus including the same

  [Link]
  Seung Wook Lee, Jae Wook Lee, Young Hwan Oh, Seng Hak Kim, Tae Jun Ham
  US Patent 12,277,440 (2025)
• Processor, method of operating the processor, and electronic device including the same

  [Link]
  Seung Wook Lee, Jaeyeon Won, Jae Wook Lee, Tae Jun Ham
  US Patent 12,327,179 (2025)
• Layer-wise scheduling on models based on idle times

  [Link]
  Seung Wook Lee, Younghwan Oh, Jaewook Lee, Sam Son, Yunho Jin, Tae Jun Ham
  US Patent 12,099,869 (2024)
• Hardware accelerator performing search using inverted index structure and search system including the hardware accelerator

  [Link]
  Jun Heo, Jaeyeon Won, Yejin Lee, Jaeyoung Jang, Tae Jun Ham, Jae Wook Lee
  US Patent 11,544,270 (2023)
• Hammer refresh row address detector, and semiconductor memory device and memory module including the same

  [Link]
  Hoon Shin, Yeonhong Park, Jaewook Lee, Eojin Lee, Woosuk Kwon, Jungho Ahn, Tae Jun Ham
  US Patent 11,568,917 (2023)
• Method for candidate selection and accelerator for performing candidate selection

  [Link]
  Tae Jun Ham, Seonghak Kim, Sungjun Jung, Younghwan Oh, Jaewook Lee, Deog-Kyoon Jeong, Minsoo Lim
  US Patent 11,636,173 (2023)
• Device for accelerating self-attention operation in neural networks

  [Link]
  Ye Jin Lee, Tae Jun Ham, Seong Hoon Seo, Soo Sung Kim, Hyun Ji Choi, Jae W. Lee, Sung Jun Jung
  US Patent App. 17/864,235 (2023)
• Accelerator system for training deep neural network model using nand flash memory and operating method thereof

  [Link]
  Jae W. Lee, Yunho Jin, Jong Hyun Bae, Gin A Sohn, Tae Jun Ham
  US Patent App. 18/089,141 (2023)
• Method for processing page fault by processor

  [Link]
  Jinkyu Jeong, Jae Wook Lee, Wenjing Jin, Tae Jun Ham
  US Patent 11,436,150 (2022)
• Electronic device and method with scheduling

  [Link]
  Seung Wook Lee, Younghwan Oh, Jaewook Lee, Sam Son, Yunho Jin, Tae Jun Ham
  US Patent App. 17/195,748 (2022)
• Instruction, Circuits, and Logic for Graph Analytics Acceleration

  [Link]
  Lisa K. Wu, Tae Jun Ham, Narayanan Rajagopalan Satish, Narayanan Sundaram
  US Patent App. 15/089,232 (2017)

Professional Service

• MICRO: Program Committee (2026), External Review Committee (2025), External Review Committee (2024), Student Research Competition Selection Committee (2023)
• HPCA: Program Committee (2025, 2026), Industry Track Program Committee (2026)
• ISCA: Program Committee (2025), External Review Committee (2024)
• ASPLOS: Program Committee (2023, 2024), External Review Committee (2019)
• IISWC: Program Committee (2024)
• YArch: Program Committee (2024)
• IEEE Micro Top Picks: Program Committee (2023)
• CGO: Web Chair (2021, 2022)
• Journal Reviews: IEEE Transactions on Computers (TC), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Mobile Computing (TMC), IEEE Computer Architecture Letters (CAL), IEEE Micro, ACM Transactions on Architecture and Code Optimization (TACO), ACM Transactions on Parallel Computing (TOPC), Elsevier Future Generation Computer Systems (FGCS)

Selected Talks

• POSTECH Summer AI Seminar (2020): Hardware/Software Co-design for Modern AI and Data Analytics Applications
• Seoul National University AI Summer School (2020): Accelerating Neural Network Attention Mechanism with HW/SW Codesign
• HiPEAC Conference (2020): Efficient Data Supply for Parallel Heterogeneous Architectures
• DARPA HIVE PI Meeting (2017): Graphicionado: A High-Performance and Energy-Efficient Accelerator for Graph Analytics
• KAIST/POSTECH (2017): DeSC: Decoupling Data Supply from Computation for Latency-Tolerant Communication

Research Mentoring & Supervision

During my tenure as a postdoctoral researcher at Seoul National University, I closely mentored and collaborated with the following students (in partnership with Prof. Jae W. Lee), overseeing research projects from initial concept through system implementation to high-impact publication.